Those skilled in the art understand that integrated circuit dimensions are becoming increasingly smaller. As the technology nodes for fabrication continue to scale down, it is becoming increasingly more difficult to prevent short channel effects (SCE) in the transistor and reduce the resistance of metal lines in order to reach required performance characteristics for device speed performance. Additionally, the reduced pitch of the transistor layout complicates the ability to make electrical contact to the source and drain regions from above the transistor.
It is known in the art to fabricate transistors on an integrated circuit substrate which is of the Silicon-on-Insulator (SOI) type (as opposed to the use of bulk semiconductor substrates). An SOI substrate is formed of a top semiconductor (for example, silicon or silicon-germanium) layer over an insulating (for example, silicon dioxide) layer over a bottom semiconductor (for example, silicon) substrate layer. The source, drain and channel of the transistor are formed in the top semiconductor layer. The resulting transistor is electrically insulated from the lower part of the substrate by the intermediate layer of insulating material. This structure advantageously reduces concerns with leakage current.
Further substrate development has reduced the thickness of the intervening insulating layer to about 50 nm to produce a substrate for use in transistor fabrication that is referred to as an extremely thin silicon on insulator (ETSOI) substrate. Still further substrate development has reduced the thicknesses of all substrate layers to produce a substrate for use in transistor fabrication that is referred to an ultra-thin body and buried oxide (UTBB) substrate where the thickness of the intervening insulating layer is about 25 nm (or less) and the thickness of the top semiconductor layer is about 5 nm to 10 nm. All of these substrates may more generally be referred to as SOI substrates.
Notwithstanding the recognized advantages of using SOI substrates for transistor fabrication, it is noted that some variation in layer thickness can occur, especially in the case of the ETSOI substrate and the UTBB substrate. This variation in layer thickness can lead to variability in both threshold voltage (Vt) roll-off and sub-threshold voltage slope for transistors fabricated on and in the substrate. This variability is especially a concern for transistors having gate lengths of less than about 25 nm.
There is accordingly a need in the art for an alternative means to make a transistor supported by a SOI-type substrate.